1. Field
Exemplary embodiments relate to a technology for generating an assertion and verifying a processor using the assertion.
2. Description of the Related Art
Functional verification of a processor in the related art means a verification to check whether an architecture specification of a processor and a processor designed at a Resister Transfer Level (RTL) logically perform the same operation. Verification test cases in the related art, such as a regression test and a random text, are applied in verifying a designed processor. In addition, test coverage is measured to check whether various design functions have been verified.
Text coverage in the related art is largely divided into code coverage and functional coverage. Code coverage is an indicator of how thoroughly a designed code is tested during simulation of a text case, and functional coverage is an indicator of whether a function that an engineer wants to measure is executed.
Functional coverage is a method for measuring whether an assertion is executed by designing the assertion for an operation that has to be performed or that should not be performed among the processor operations that the engineer wants to measure.
In assertion based verification (ABV), an assertion is inserted into a designed processor and the processor, into which the assertion is inserted, is simulated. During simulation of the processor, it is easy to find an error detected point by monitoring and checking the inserted assertion, so that verification time may be reduced.
However, an assertion in the related art has to be designed by a user based on the architecture specification of a processor and needs to be redesigned whenever the architecture specification is changed. In addition, in the related art, it is necessary to verify whether the assertion is properly designed. Thus, a lot of time and effort is required to design an assertion.